Native pmos device with low threshold voltage and high drive current and method of fabricating the same

ABSTRACT

A native p-type metal oxide semiconductor (PMOS) device that exhibits a low threshold voltage and a high drive current over a varying range of short channel lengths and a method for fabricating the same is discussed in the present disclosure. The source and drain regions of the native PMOS device, each include a strained region, a heavily doped raised region, and a lightly doped region. The gate region includes a stacked layer of a gate oxide having a high-k dielectric material, a metal, and a contact metal. The high drive current of the native PMOS device is primarily influenced by the increased carrier mobility due to the strained regions, the lower drain resistance due to the raised regions, and the higher gate capacitance due to the high-k gate oxide of the native PMOS device.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.13/741,157, filed Jan. 14, 2013, which is hereby incorporated byreference in its entirety.

BACKGROUND OF THE DISCLOSURE

1. Field of the Disclosure

The present disclosure generally relates to semiconductor devices, andmore specifically to native p-type metal oxide silicon (PMOS) deviceshaving low threshold voltage and high drive current.

2. Background Art

Metal oxide semiconductor field effect transistor (MOSFET) devices aregenerally fabricated using conventional complementary metal oxidesilicon (CMOS) foundry technology. The conventional CMOS logic foundrytechnology accommodates a minimum size, such as a length, width, and/orheight of the regions of the semiconductor devices as defined by one ormore minimum design rules (MDRs). These minimum design rules representlimits to resolution of processing used by the conventional CMOS logicfoundry technology, such a minimum space interval between one or morephotolithographic masks used to manufacture the semiconductor devices.

A conventional MOSFET device generally includes a source region, a drainregion, a gate between the source and drain regions, and a channelregion below the gate region. A minimum voltage, called the thresholdvoltage, is required at the gate for the device to turn “on”. A drivecurrent, also referred to as a drain current, flows between the sourceand drain regions through the channel region when a gate potential abovethe threshold voltage is applied, and potentials at the source and drainregions are applied. MOSFET devices can be fabricated to be P-type orN-type devices. A P-type metal oxide semiconductor field effecttransistor (PMOSFET) device, for example, can be fabricated byimplanting phosphorus atoms into a P-type substrate to create an N-well.P+ regions are formed in the N-well to provide source and drain regions.A PMOSFET device may be interchangeably referred to herein as PMOSdevice or PMOSFET device.

With the advance in semiconductor technology and the increasing need forhigh speed systems with low power consumption, there has been continuedscaling down of MOSFET devices using CMOS foundry technology withdecreasing MDRs to accommodate a larger number of MOSFET devices onsmaller systems. However, the scaling down of MOSFET devices to smallerdimensions can introduce short channel effects in the devices due to theshort channel lengths (about approximately 100 nm or less) of the scaleddown MOSFET devices. Short channel effects can cause degradation in theperformance of the MOSFET device due to, for example, but not limited tothe loss of gate control over the threshold voltage which can result inthe device being mostly in the “on” state and the degradation of carriermobility which results in lower drive current.

The foregoing problem with the threshold voltage has been addressed inU.S. patent application Ser. No.: 10/911,720, filed on Aug. 5, 2004, nowU.S. Pat. No. 7,161,213 and U.S. patent application Ser. No.:11/648,651, filed on Jan. 3, 2007, now U.S. Pat. No. 7,382,024, all ofwhich are incorporated herein by reference in their entirety. In theaforementioned applications, a conventional native PMOS device having alow threshold voltage has been described. The conventional native PMSOdevice includes a P+ polysilicon gate, halo implants, lightly dopedregions in the source and drain regions, and heavily doped regions inthe source and drain regions. The halo implants and the doped regions ofthe source and drain regions primarily enable low threshold voltagecharacteristics of the conventional native PMOS device.

With the continued scaling down of MOSFET devices, there is still anongoing need for a MOSFET device that maintains a stable thresholdvoltage and exhibits a high drive current over a varying range of shortchannel lengths. At the same time, for a MOSFET device to have a largeoperating voltage range, it is necessary for the threshold voltage to beclose to zero volts.

BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES

The accompanying drawings illustrate the present disclosure and,together with the description, further serve to explain the principlesof the disclosure and to enable one skilled in the pertinent art to makeand use the disclosure.

FIG. 1 illustrates a cross-sectional view of a native P-type metal oxidesemiconductor (PMOS) device according to a first embodiment of thepresent disclosure.

FIG. 2 illustrates a horizontal energy band diagram according to anembodiment of the present disclosure.

FIG. 3 illustrates a horizontal energy band diagram depictingpunch-through according to an embodiment of the present disclosure.

FIG. 4 illustrates a cross-sectional view of a short channel native PMOSdevice according to an embodiment of the present disclosure.

FIG. 5 illustrates a vertical energy band diagram according to anembodiment of the present disclosure.

FIG. 6 illustrates a flat-band condition of a native PMOS deviceaccording to an embodiment of the present disclosure.

FIG. 7 illustrates a cross-sectional view of a native PMOS deviceaccording to a second embodiment of the present disclosure.

FIG. 8 illustrates a flow chart for a method of processing a native PMOSdevice according to a first embodiment of the present disclosure.

FIG. 9 further illustrates a flow chart for a method of processing anative PMOS device according to a second embodiment of the presentdisclosure.

FIG. 10 illustrates a first exemplary configuration of a native PMOSdevice according to an embodiment of the present disclosure.

FIG. 11 illustrates a second exemplary configuration of a native PMOSdevice according to an embodiment of the present disclosure.

FIG. 12 illustrates a third exemplary configuration of a native PMOSdevice according to an embodiment of the present disclosure.

The present disclosure will now be described with reference to theaccompanying drawings. In the drawings, like reference numbers generallyindicate identical, functionally similar, and/or structurally similarelements. The drawing in which an element first appears is indicated bythe leftmost digit(s) in the reference number.

DETAILED DESCRIPTION OF THE DISCLOSURE

The following Detailed Description refers to accompanying drawings toillustrate exemplary embodiments consistent with the present disclosure.References in the Detailed Description to “one exemplary embodiment,”“an exemplary embodiment,” “an example exemplary embodiment,” etc.,indicate that the exemplary embodiment described can include aparticular feature, device, or characteristic, but every exemplaryembodiment can not necessarily include the particular feature, device,or characteristic. Moreover, such phrases are not necessarily referringto the same exemplary embodiment. Further, when a particular feature,device, or characteristic is described in connection with an exemplaryembodiment, it is within the knowledge of those skilled in the relevantart(s) to effect such feature, device, or characteristic in connectionwith other exemplary embodiments whether or not explicitly described.Furthermore, it should be understood that spatial descriptions (e.g.,“above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,”“vertical,” “horizontal,” etc.) used herein are for purposes ofillustration only, and that practical implementations of the devicesdescribed herein can be spatially arranged in any orientation or manner.

The exemplary embodiments described herein are provided for illustrativepurposes, and are not limiting. Other exemplary embodiments arepossible, and modifications can be made to the exemplary embodimentswithin the spirit and scope of the present disclosure. Therefore, theDetailed Description is not meant to limit the present disclosure.Rather, the scope of the present disclosure is defined only inaccordance with the following claims and their equivalents.

The following Detailed Description of the exemplary embodiments will sofully reveal the general nature of the present disclosure that otherscan, by applying knowledge of those skilled in relevant art(s), readilymodify and/or adapt for various applications such exemplary embodiments,without undue experimentation, without departing from the spirit andscope of the present disclosure. Therefore, such adaptations andmodifications are intended to be within the meaning and plurality ofequivalents of the exemplary embodiments based upon the teaching andguidance presented herein. It is to be understood that the phraseologyor terminology herein is for the purpose of description and not oflimitation, such that the terminology or phraseology of the presentspecification is to be interpreted by those skilled in relevant art(s)in light of the teachings herein.

The example embodiments described herein are provided for illustrativepurposes, and are not limiting. Further structural and operationalembodiments, including modifications/alterations, will become apparentto persons skilled in the relevant art(s) from the teachings herein.

Embodiments of native PMOS devices of the present disclosure areprocessed using smaller CMOS logic foundry technologies than that usedfor processing the conventional native PMOS. These embodiments of thepresent disclosure are characterized as having higher drive current(also referred herein as drain current) when compared to the drivecurrent of the conventional native PMOS while maintaining a lowthreshold voltage similar to the threshold voltage of the conventionalnative PMOS.

A NATIVE PMOS ACCORDING TO A FIRST EMBODIMENT OF THE PRESENT DISCLOSURE

FIG. 1 illustrates a cross-sectional view of a native PMOS device 100according to a first embodiment of the present disclosure. The nativePMOS device 100 includes a substrate 155, a deep N-well 150, N-wells 145and 146, P-wells 147 and 148, shallow trench isolation (STI) regions 135and 136, a source region 101, a drain region 102, a gate region 105, achannel region 106, spacers 125 and 130, halo implants 160 and 165, andstrained regions 170 and 175.

The substrate 155 can be a silicon (Si) substrate on which the nativePMOS device 100 can be formed. The substrate 155 can be implanted withp-type carriers to be a P-type Si substrate. The p-type carriers areprovided by p-type materials, such as, but not limited to, boron oraluminum to provide some examples. The deep N-well 150 can be positionedto divide the substrate 155 laterally into substrate regions 155 a and155 b, with the region 155 a between and in substantial contact with thegate region 105 and the deep N-well 150.

The deep N-well 150 can be formed by doping the substrate with n-typecarriers using n-type materials, such as, but not limited to phosphorus,arsenic, or antimony to provide some examples. In an example of thefirst embodiment, the deep N-well 150 can be positioned at least betweenapproximately 0.3 and approximately 0.5 μm below a top side 155 c of thesubstrate 155 to prevent a “tail” of a Gaussian carrier distribution inthe deep N-well 150 from substantially effecting a carrier concentrationof the substrate region 155 a. For example, n-type carriers from thedeep N-well 150 can form a heavily doped N-well in the substrate region155 a if the deep N-well is positioned less than approximately 0.3 μmbelow the top side 155 c. This heavily doped N-well may result in alarge threshold voltage of the native PMOS device 100. In an example ofthis embodiment, the substrate region 155 a can be a lightly dopedn-type region.

Generally, doping a material with a comparatively small dopingconcentration of carriers, approximately 10¹⁶ to 10¹⁸/cm³ refers to adoping that is low or light. Similarly, doping a material with acomparatively large doping concentration of carriers equal or greaterthan 10¹⁹/cm³, refers to a doping that is high or heavy.

In one example of this embodiment, the deep N-well 150 can extendlaterally beyond the inner perimeter sides 145 a and 146 b of therespective N-wells 145 and 146, such that a first side 150 a and asecond side 150 b of the deep N-well 150 is positioned between the innerperimeter sides 145 a and 146 a and the outer perimeter sides 145 b and146 b of the N-wells 145 and 146, respectively. In another example ofthis embodiment, the deep N-well 150 can extend laterally beyond theouter perimeter sides 145 b and 146 b of the N-wells 145 and 146, suchthat the deep N-well 150 serves as a common deep N-well for severalother devices formed on the substrate 155.

The N-wells 145 and 146 can be formed, for example, by doping thesubstrate 155 with n-type carriers. The n-type material used for dopingthe N-wells 145 and 146 can be similar to or different than the n-typematerial used for the deep N-well 150. In an example of the firstembodiment, the N-wells 145 and 146 can be doped more heavily than thedeep N-well 150. The vertical dimension of the N-wells 145 and 146 canbe smaller than the vertical dimension of the deep N-well 150, accordingto an example of the first embodiment. Although the N-wells 145 and 146are depicted as two separate N-wells in the cross-sectional view of thedevice 100 in FIG. 1, the N-wells 145 and 146 can represent a single,concentric N-well with a continuous inner perimeter side and acontinuous outer perimeter side (not shown). The device 100 can includeany suitable number of N-wells, for example.

The native PMOS device 100 can be a part of a complementary metal oxidesemiconductor (CMOS) device. In a CMOS device, PMOS and N-type metaloxide semiconductor (NMOS) devices are electrically coupled, such thatthe combination of PMOS and NMOS devices typically use less power thanPMOS or NMOS devices operating independently. Both the deep N-well 150and the N-wells 145 and 146 can provide isolation for the native PMOSdevice 100 from an adjacent NMOS device (not shown). For example, thedeep N-well 150 and/or the N-wells 145 and 146 can prevent or hinder anyparasitic effects between the PMOS device 100 and any adjacent devicesfabricated on the substrate 155. Atoms in the deep N-well 150 and/or theN-wells 145 and 146 can form bonds with carriers as the carriers migratefrom one device toward another. In addition, the deep N-well 150 canelectrically isolate the substrate regions 155 a and 155 b from eachother. For instance, the deep N-well 150 can provide electricalisolation in the vertical direction with respect to the two-dimensionalrepresentation of the native PMOS device 100 in FIG. 1.

STI regions 135 and 136 can provide isolation and protection for thenative PMOS device 100. For instance, the STI region 135 can provideisolation in the lateral direction with respect to the two-dimensionalrepresentation of the native PMOS device 100 in FIG. 1. The STI regions135 and 136 can be formed of a dielectric material (e.g., SiO₂), thoughany suitable insulating material can be used. For instance, bipolartechnologies sometimes use polysilicon, rather than SiO₂. Although theSTI regions 135 and 136 are depicted as two separate STI regions in thecross-sectional view of the device 100 in FIG. 1, the STI regions 135and 136 can represent a single, concentric STI region with a continuousinner perimeter side and a continuous outer perimeter side (not shown),according to an example of this embodiment. In another example of thisembodiment, the STI regions 135 and 136 can be two separate regions.

The source region 101 of the native PMOS device 100 can be formed toinclude a strained region 170, an LDD (lightly doped drain) region 180,and an HDD (heavily doped drain) region 190. The drain region 102 can beformed to include a strained region 175, an LDD region 185, and an HDDregion 195. The region between the outer edges of the source region 101and the drain region 102 of the device 100 is commonly referred to as anactive region 107. More specifically, the region between a second side190 b of the HDD region 190 and a second side 195 b of the HDD region195 is the active region 107 of the device 100. The drain current of thenative PMOS device 100 is primarily due to carriers flowing within theactive region 107 in a channel region 106 located below the gate region105 and between the source region 101 and the drain region 102.

The strained regions 170 and 175 can be formed to enhance performance ofthe native PMOS device 100 that can include enhancing the mobility ofcarriers in the channel 106 and as a result enhancing the drain current.The strained regions 170 and 175 can be formed with a material having alattice structure that is dissimilar to the lattice structure of thesubstrate 155 material. The lattice structures of the materials of thestrained regions 170 and 175 can be larger than the lattice structure ofthe substrate 155 material. The larger lattice structures of thematerials in the strained regions 170 and 175 can push portions of thesubstrate region 155 a adjacent to a first side 170 a of the strainedregion 170 and a first side 175 a of the strained region 175 towards thechannel region 106. This can induce a uniaxial compressive strain in thechannel region 106 which may result in higher mobility of the carriersin the substrate region 155 a when compared to conventional native PMOSdevices without strained regions in the source and drain regions. In oneexample of this embodiment, a compound semiconductor, such as silicongermanium (SiGe), having a larger lattice structure than that of thesubstrate 155 material such as Si can be used to form the strainedregions 170 and 175 on the substrate 155. The lattice mismatch betweenthe SiGe regions if formed on the Si substrate 155 can introduce strainin the strained regions 170 and 175.

In an example of this embodiment, the strained region 170 can bepositioned in the substrate 155 in such a manner that a first side 170 aof the strained region 170 can be substantially aligned vertically witha first side 105 a of the gate region 105, and a second side 170 b ofthe strained region 170 is adjacent to and/or in substantial contactwith the inner perimeter side 135 a of the STI region 135. The secondstrained region 175 can be positioned in the substrate 155 in such amanner that a first side 175 a of the strained region 175 can besubstantially aligned vertically with a second side 105 b of the gateregion 105, and a second side 175 b of the strained region 175 isadjacent to and/or in substantial contact with the inner perimeter side136 a of the STI region 136.

The LDD regions 180 and 185 can be doped with p-type carriers usingp-type materials, such as, but not limited to boron or aluminum. In anexample of this embodiment, the LDD regions 180 and 185 can beapproximately 100 nm in vertical dimensions and are typically referredto as shallow regions. The shallow LDD regions 180 and 185 can reduce anelectric field under the gate region 105 and maintain a stable lowthreshold voltage over a wide range of channel lengths of the nativePMOS device 100.

The LDD region 180 can be positioned in the substrate 155 in such amanner that a first portion of the LDD region 180 can be in the strainedregion 170 and a second portion of the LDD region 180 extends laterallyout of the strained region 170. Similarly, the LDD region 185 can bepositioned in the substrate 155 in such a manner that a first portion ofthe LDD region 185 can be in the strained region 175 and a secondportion of the LDD region 185 extends laterally out of the strainedregion 175. The extended out portions of the LDD regions 180 and 185,can be positioned below the gate region 105 and be in substantialcontact with different portions of the gate region 105, according to anexample of this embodiment.

The HDD regions 190 and 195 can be formed by doping the substrate 155with p-type carriers using p-type materials, such as, but not limited toboron or aluminum. The p-type carrier concentration in the HDD regions190 and 195 can be higher than the p-type carrier concentrations of theLDD regions 180 and 185 for example. The HDD region 190 can bepositioned in the strained region 170 in such a manner that a first side190 a and a second side 190 b is adjacent to and/or in substantialcontact with the LDD region 180 and a portion of the STI region 135,respectively. Similarly, the HDD region 195 can be positioned in thestrained region 175 in such a manner that a first side 195 a and asecond side 195 b is adjacent to and/or in substantial contact with theLDD region 185 and a portion of the STI region 136, respectively. Eventhough, the vertical dimensions of the HDD regions 190 and 195 are shownto be smaller than the vertical dimension of the strained regions, 170and 175, in FIG. 1, the vertical dimensions of the HDD regions 190 and195 and the strained regions 170 and 175 can be equal to each other inan example of this embodiment. The vertical dimensions of the HDDregions 190 and 195 can be larger than the vertical dimensions of therespective LDD regions, 180 and 185 in another example of thisembodiment.

The gate region 105 of the native PMOS device 100 can be positionedbetween the source region 101 and the drain region 102 of the device100. The lateral dimension between the first and second sides 105 a and105 b of the gate region 105 is commonly referred to as the gate length.In an example of this embodiment, the gate region 105 includes a gateoxide layer 110, a metal layer 115, and a contact metal layer 120. Thegate region 105 can be configured with equal lengths of the gate oxidelayer 110, the metal layer 115, and the contact metal layer 120, wherethe length of each layer represents its respective lateral dimensionbetween the first and second sides 105 a and 105 b of the gate region105. The lateral dimension of the metal layer 115 can be greater thanthe lateral dimension of the contact metal layer 120, according to anexample of this embodiment.

The contact metal layer 120 can be positioned above and in substantialcontact with the metal layer 115. One or more materials having lowcontact resistances, such as, but not limited to aluminum or copper canbe used for the fabrication of the contact metal layer 120. The contactmetal layer 120 serves, for example, as a contact pad for the couplingof the native PMOS device 100 with other devices or peripheralcircuitry. The metal layer 115 can represent a metal gate or a gateelectrode of the native PMOS device 100. The metal layer 115 can bepositioned between and in substantial contact with the contact metallayer 120 and the gate oxide layer 110. In one example of thisembodiment, the metal layer 115 can be deposited at a thickness smallerthan the thickness of the contact metal layer 120. The material used toform the metal layer 115 can be any metal with a work functioncomparable to P+ polysilicon. For example, but not limited to tungstenor titanium can be used to form the metal layer 115. The use of themetal gate layer can allow, low temperature processing of the device 100using a CMOS logic foundry technology when compared to the processingtemperature of the conventional native PMOS device. A conventional P+polysilicon gate typically requires higher processing temperature due toannealing process than the metal gate processing temperature. Lowtemperature processing can help to reduce heat induced stress in thematerials of the native PMOS device 100 that may result in variation ofthe characteristic of the device 100.

The gate oxide layer 110 can be positioned between and in substantialcontact with the top side 155 c of the substrate 155 and the metal layer115. A high dielectric constant (high-k dielectric) gate oxide having athickness approximately in a range between approximately 2 nm andapproximately 5 nm can be used as the gate oxide layer 110. A high-kdielectric refers to an insulating material having a dielectric constantlarger than SiO₂. The gate oxide layer 110 can be formed using at leasta high-K dielectric material having a dielectric constant between 10 and30 such as, but not limited to, hafnium dioxide or zirconium dioxide toprovide some examples. Capacitors formed with high-k materials aretypically characterized with higher capacitance than capacitors withSiO₂. For instance, using the high-k gate oxide layer 110 in the nativePMOS device 100 can provide a higher gate oxide capacitance, C_(OX),between the metal gate 115 and the substrate 155 a or the channel region106 when compared to the gate oxide capacitance obtained for a similargate oxide thickness in the conventional native PMOS device. Thus, for asimilar gate oxide capacitance, thicker high-k gate oxide layer 110 canbe used in the device 100 than the gate oxide in the conventional nativePMOS. Thicker high-k gate oxide layer 110 can help to reduce leakage dueto tunneling of carriers between the metal gate 115 and the substrateregion 155 a, in an example of this embodiment.

According to an example of this embodiment, applying a first potential,such as a negative voltage to the gate region 105 and a secondpotential, such as a ground potential to the HDD region 190 of thesource region 101 can cause the p-type carriers below the gate region105 to form a channel region 106 between the LDD region 180 of thesource region 101 and the LDD region 185 of the drain region 102. When athird potential, such as a negative voltage is applied to the HDD 195 ofthe drain region, the p-type carriers accumulated in the channel regioncan allow a current to flow from the source region 101 to the drainregion 102 of the native PMOS device 100. This current is typicallyreferred to as the drain current. The drain current can be influenced,for example, by the mobility of p-type carriers in the channel region106 and the gate capacitance, Cox, of the native PMOS device 100.Improving the mobility of p-type carriers in the channel region 106 andincreasing the gate capacitance, Cox, can increase the drain current.For example, the drain current of the native PMOS device 100 is higherthan the drain current of the conventional native PMOS device since theuse of the strained regions 170 and 175 can improve the mobility ofp-type carriers in the native PMOS device 100, and the use of high-kgate oxide can improves the gate oxide capacitance of the native PMOSdevice 100.

The native PMOS device 100 can include spacers 125 and 130 above therespective LDD regions 180 and 185 and in substantial contact with therespective first and second sides 105 a and 105 b of the gate region105. The spacers 125 and 130 can be formed using a dielectric material,such as SiO₂, though any suitable insulating material can be used.

According to an embodiment, a voltage at the gate region 105 generatesan electric field, which depletes the channel region 106 or a portion ofthe channel region 106 of free carriers. The region of the channelregion 106 that is depleted of free carriers is referred to as thedepletion region of the native PMOS device 100. If a negative voltage isapplied to the gate region 105, for example, the depletion region canspread in the channel region 106 from the LDD and HDD regions 185 and195 of the drain region 102 toward the LDD and HDD regions 180 and 190of the source region 101. If the depletion region reaches the sourceregion 101, then “punchthrough” can occur. For instance, the gate region105 can no longer be able to control the drain current from the sourceregion 101 to the drain region 102.

Halo implants 160 and 165 can be formed to prevent punchthrough in thenative PMOS device 100. For example, the halo implants 160 and 165 canhinder the depletion region from reaching the HDD region 190 of thesource region 101 when the depletion region extends through the channelregion 106. The halo implants 160 and 165 can be doped with phosphorusatoms or arsenic atoms, to provide some examples. The halo implants 160and 165 can be typically doped more heavily than the N-wells 145 and146. Deep submicron PMOS devices often include halo implants 160 and 165also referred to as “pockets”.

FIG. 2 illustrates a horizontal energy band diagram 200 according to anembodiment of the present disclosure. The horizontal energy band diagram200 includes a conduction energy band (E_(C)) 210 a and a valence energyband (E_(V)) 210 b. The fermi energy level (E_(f)) is the energy levelhaving approximately a fifty percent probability of being filled with acarrier at equilibrium. The energy band 210 b is at a higher electronenergy at point 220 as compared to points 230 because the halo implants160 and 165 increase the barriers at points 230. A higher barriergenerally allows fewer carriers to pass. For example, the halo implants160 and 165 can reduce the leakage current between the source region 101and the drain region 102.

FIG. 3 illustrates a horizontal energy band diagram 300 depictingpunchthrough according to an embodiment of the present disclosure. InFIG. 3, the HDD region 190 of the source region 101 is biased to groundfor illustrative purposes. The HDD region 195 of the drain region 102 isnegatively biased, such that the depletion region 340 extends from theHDD region 190 of the source region 101 and touches the HDD region 195of the drain region 102. The energy bands 310 can shift in response tothe depletion region contacting the HDD region 190 of the source region101, and as a result holes can be allowed to pass from the source region101 to the drain region 102.

In a non-equilibrium condition, the fermi energy level E_(f) differs forelectrons and holes, resulting in an electron quasi-fermi level (E_(fn))and a hole quasi-fermi level (E_(fp)). As shown in FIG. 3, negativelybiasing the drain region can create a non-equilibrium condition, whichshifts the energy bands E_(C), E_(V), and E_(f) of the energy banddiagram 300. The difference between E_(fn) and E_(fp) is directlyproportional to the bias voltage (V) applied to the HDD region 195. Thisdifference is represented by the equation E_(fn)−E_(fp)=q_(e)V, whereq_(e) is the charge of an electron.

Referring back to FIG. 1, in absence of punchthrough, the magnitude ofthe voltage at the gate region 105 may have to exceed a thresholdvoltage of the native PMOS device to allow carriers, such as holes orelectrons, to flow from the source region 101 to the drain region 102,or vice versa. According to an embodiment, the native PMOS device 100has a positive threshold voltage. For example, the threshold voltage canbe approximately +300 mV to +500 mV. In this example, the native PMOSdevice 100 can turn on in response to the gate voltage going belowapproximately +300 mV to +500 mV.

The threshold voltage is based on characteristics of the native PMOSdevice 100. For example, the distance between the halo implants 160 and165 is generally directly proportional to the threshold voltage of thenative PMOS device 100. Referring to the embodiment of FIG. 4, the haloimplants 160 and 165 can touch each other. For instance, the haloimplants 160 and 165 can combine to form a single halo implant. Thecombined halo implant can provide the same function as an N-well of aconventional PMOS device. In FIG. 4, the native PMOS device 400 can havea threshold voltage of approximately zero volts.

According to an embodiment, the channel length of the native PMOS device100, 400 can affect the threshold voltage of the native PMOS device 100,400. For example, a shorter channel length can necessitate that the haloimplants 160 and 165 be closer together.

Turning now to FIG. 5, a vertical energy band diagram 500 representsenergy bands 510 of the gate region 105 and the substrate 155, forexample a P-type substrate. In FIG. 5, the native PMOS device 100, 400is at equilibrium. No voltage is applied at the gate region 105. Thevoltage at the gate region 105 is approximately zero. E_(C) and E_(V)represent the edges of the conduction band 510 a and the valence band510 b, respectively. E_(i) represents the intrinsic fermi level E_(fm)and E_(fs) represent the fermi levels in the metal gate and thesubstrate, respectively. In FIG. 5, the energy bands 510 of thesubstrate 155 bend in the direction of higher electron energy (i.e.lower electrostatic potential) at the junction between the gate oxidelayer 110 and the P-substrate 155.

FIG. 6 illustrates a flatband condition of the native PMOS device 100,400 according to an embodiment of the present disclosure. For instance,applying a negative voltage at the gate region 105 can flatten theenergy bands 510, as shown in FIG. 6. According to an embodiment, anegative voltage at the gate region 105 can reduce the electron energyat the junction between the gate oxide layer 110 and the P-substrate155.

The threshold voltage of a conventional PMOS device can be expressed by:

V_(t)=Φ_(ms)−(Q _(SS) /C _(OX))−(Q _(B) /C _(OX))−2Φ_(f),  (1)

where Φ_(ms)=Φ_(m)−Φ_(s), Φ_(m) is based on the type of material usedfor the gate region 105, and Φ_(s) is based on the type of material usedfor the substrate 155. For example, referring back to FIGS. 1 and 4, thegate region 105 is a metal, and the substrate 155 is P-type. Q_(SS)represents the fixed charges in the gate oxide layer 110. Φ_(ms) andQ_(SS) can be used to calculate the flat band voltage of the native PMOSdevice 100. C_(OX) represents the capacitance between the gate region105 and the P-type substrate 155. In FIG. 6, q represents the charge ofan electron and equals approximately 1.602×10⁻¹⁹ C and 2Φ_(f) representsthe onset of inversion with respect to band bending. Inversion refers tothe accumulation of charge at the surface of the substrate 155. Forexample, if charge is accumulated at the surface of the substrate 155,then the energy bands 510 typically bend upward or downward. If theenergy bands 510 are flat, then charge is generally not accumulated atthe surface of the substrate 155.

Q_(B) represents the depletion charge contributed by the N-well 145 atthe onset of inversion. Because the wells are N-type in this example,Q_(B) is a positive (i.e. donor-type) charge.

If the native PMOS device 100, 400 includes halo implants 160 and 165 asshown in FIGS. 1 and 4, the threshold voltage is further based on thedepletion charge Q_(h) at the surface of the halo implants, 160 and 165.For example, charge can accumulate at the interface between halo implant160 and the HDD region 190 and/or halo implant 165 and the HDD region195. Taking Q_(h) into consideration, the threshold voltage can berepresented by as:

V_(t)=Φ_(ms)−(Q _(SS) /C _(OX))−(Q _(B) /C _(OX))−2Φ_(f)−(Q _(h) /C_(OX)).  (2)

The native PMOS device 100, 400 can have N-wells 145 and 146 that do notextend completely across the active region 107. The material beneath thegate oxide layer 110 can be P-type substrate 155. Charge Q_(psub) fromthe P-substrate 155 can contribute to the threshold voltage, asindicated by:

V_(t)=Φ_(ms)−(Q _(SS) /C _(OX))−(Q _(B) /C _(OX))−2Φ_(f)−(Q _(h) /C_(OX))+(Q _(psub) /C _(OX)).  (3)

Referring to FIG. 1 for illustrative purposes, the Q_(psub) and Q_(B)charges generally dominate the threshold voltage calculation for anative PMOS device 100 having a long channel region 106. The thresholdvoltage of a long channel device (e.g., a device having a channel lengthof approximately 1 μm or greater) is, therefore, typically positive. Forinstance, the threshold voltage of a long channel device can beapproximately 300-500 mV. At the onset of inversion, most of the Q_(B)charge is contributed by the deep N-well 150 because the N-wells 145 and146 generally do not extend substantially into the active region.

Referring to FIG. 4, the Q_(h) charge contributed by the halo implants160 and 165 can have a more significant impact on the threshold voltagefor a native PMOS device 400 that has a short channel region 106. Forexample, if the channel region length is reduced, then Q_(B) and C_(OX)decrease, but Q_(h) remains substantially the same. Q_(B) and C_(OX) areboth area-dependent. In the embodiments of FIGS. 1 and 4, Q_(B) andC_(OX) are dependent on the area under the gate region 105. As the areaunder the gate is reduced, Q_(B) and C_(OX) decrease proportionally.Thus, the ratio of Q_(B)/C_(OX) does not vary substantially based on thechannel region length of the native PMOS device 100, 400. As the channelregion length is reduced, the ratio of Q_(h)/C_(OX) increases, becauseQ_(h) remains substantially the same. However, as the channel regionlength is reduced, the threshold voltage becomes less positive. In anembodiment, the native PMOS device 400 has a threshold voltage ofapproximately zero volts.

A NATIVE PMOS ACCORDING TO A SECOND EMBODIMENT OF THE PRESENT DISCLOSURE

A CMOS logic foundry technology fabricates the native PMOS device 700 ina similar manner as the native PMOS device 100 as described above.Therefore, only differences between the native PMOS device 700 and thenative PMOS device 100 are to be described in further detail.

As shown in FIG. 7, the source region 701 of the native PMOS device 700can be formed to include an LDD region 180, a raised region 790, and thestrained region 170, and the drain region 702 can be formed to includean LDD region 185, a raised region 795, and the strained region 175.

In an example of this embodiment, the LDD region 180 can be positionedin the substrate 155 in such a manner that a first portion of the LDDregion 180 is in the strained region 170 and a second portion of the LDDregion 180 extends laterally out of the strained region 170. Similarly,the LDD region 185 can be positioned in the substrate 155 in such amanner that a first portion of the LDD region 185 is in the strainedregion 175 and a second portion of the LDD region 185 extends laterallyout of the strained region 175. The extended out portions of the LDDregions 180 and 185 can be positioned below the gate region 105 and bein substantial contact with different portions of the gate region 105.The LDD regions 180 and 185 can be doped with p-type carriers usingp-type materials, such as, but not limited to boron or aluminum. In anexample of this embodiment, the LDD regions 180 and 185 can beapproximately 100 nm in vertical dimensions.

According to an example of this embodiment, the raised regions 790 and795 can be formed from the same material as the substrate 155 material.The raised regions 790 and 795 can be doped heavily with p-typematerial, such as, but not limited to boron or aluminum. The p-typecarrier concentration in the raised regions 790 and 795 can be higherthan the p-type carrier concentrations of the LDD regions, 180 and 185,according to an example. A first portion of the raised region 790 can bepositioned in the strained region 170 and a second portion of the raisedregion 790 can extend out vertically from the strained region 170, suchthat a top side 790 c of the raised region 790 can be at a higherelevation than the top side 155 c of the substrate 155. The firstportion of the raised region can be located between the LDD region 180and the inner perimeter side 135 a of the STI region 135. Similarly, afirst portion of the raised region 795 can be positioned in the strainedregion 175 and a second portion extends out vertically from the strainedregion 175, such that a top side 795 c of the raised region 795 can beat a higher elevation than the top side 155 c of the substrate 155. Thefirst portion of the raised region can be located between the LDD region185 and the inner perimeter side 136 a of the STI region 136. Thevertical dimensions of the extended portions of the raised regions 790and 795 are for example, approximately half of the vertical dimension ofthe gate region 105. The vertical dimensions of the first portions ofthe raised regions 790 and 795 can be equal to or less than the verticaldimensions of the respective LDD regions 180 and 185.

Deep junctions (e.g., approximately 200 nm or greater or comparable tochannel region length 106) formed between the source region 701 and thesubstrate region 155 a, and the drain region 702 and the substrateregion 155 a can increase the likelihood that the threshold voltagevaries across a range of channel region 106 lengths. Deep junctions canincrease the likelihood of the source depletion region and the draindepletion region overlap which may result in the loss of gate controlover the threshold voltage. According to an embodiment, shallow junctiondepths (e.g., approximately 50-100 nm) can provide a threshold voltagethat is relatively constant over a range of channel region 106 lengths.The raised regions 790 and 795 can help to reduce the depth of thejunction between the source region 701 and the substrate region 155 a,and between the drain region 702 and the substrate region 155 a. Forexample, the vertical dimensions of the first portions of the raisedregions 790 and 795 can be equal to or less than the shallow LDD regions180 and 185 which can be approximately 100 nm. Shallow junctionsprovided by the first portions of the raised regions 790 and 795 canreduce the possibility of the source depletion region and the draindepletion region overlap and as a result may reduce the possibility ofpunchthrough. In an example of this embodiment, the native PMOS device700 can be fabricated without the halo implants 160 and 165 since theraised regions 790 and 795 can help to prevent punchthrough.

According to an example of this embodiment, shallow first portions ofthe raised regions 790 and 795 in the respective source region 701 anddrain region 702 can help to improve the drain current of the nativePMOS device 700 by providing lower resistance (also referred herein asdrain resistance) to the flow of carriers between the source region 701and the drain region through the channel region 106 than the resistanceprovided by the HDD regions 190 and 195 in the source and drain regionsof the native PMOS device 100. In another example, the drain resistanceof the native PMOS device 700 is lower than the drain resistanceprovided by the P+ regions in the source and drain regions of theconventional native PMOS device.

A METHOD OF PROCESSING A NATIVE PMOS ACCORDING TO A FIRST EMBODIMENT OFTHE PRESENT DISCLOSURE

FIG. 8 illustrates a flow chart for a method of processing a native PMOSdevice according to a first embodiment of the present disclosure. Thenative PMOS device 100, 400 can be fabricated using, for example, CMOSlogic foundry technology with a minimum design rule of 28 nm. A deepN-well 150 is implanted in the substrate 155 at block 805. For example,a region in the substrate 155 can be doped by using an ion implantationprocess to accelerate phosphorus or arsenic atoms into the substrate 155to form the deep N-well. A shallow trench isolation (STI) layer isdefined at block 810. For instance, the STI regions 135 and 136 can beetched to provide an opening for the isolation of active PMOS elements.

The N-wells 145 and 146 are implanted at block 815. Photoresist isgenerally placed over the substrate 155 and portions of the STI layer135, though the scope of the disclosure is not limited in this respect.A mask is used to block light (e.g., ultraviolet light typically used inphotolithography) from portions of the photoresist and to expose thoseportions that are not blocked by the mask. For a positive photoresistprocess, the exposed portions of the photoresist are removed by chemicaletching, for example. For a negative photoresist process, the portionsof the photoresist that are not exposed are removed. Phosphorus orarsenic atoms are implanted into the substrate 155 in those areas notcovered by photoresist to provide the N-wells 145 and 146. The remainingphotoresist is then removed. The N-wells 145 and 146 can be insubstantial contact with the deep N-well 150. For instance, the entireperimeter of the deep N-well 150 can extend beyond the inner perimetersides 145 a and 146 a of the N-wells 145 and 146.

The gate oxide layer 110 is deposited at block 820 over the entire topside 155 c of the substrate 155. For example, the gate oxide 110 can bedeposited by atomic layer deposition or chemical vapor deposition. Atblock 825, the metal layer 115 is deposited over the gate oxide layer110, for example, by an evaporation process of metal targets or atomiclayer deposition. At block 830, a dummy polysilicon is deposited overthe metal layer 115, for example, by a chemical vapor depositionprocess. The dummy polysilicon can be replaced by the contact metallayer 120 at the end of the processing of the native PMOS device 100,400. This partial replacement of the gate region 105 can help toprotect, the integrity of the contact metal layer which can beintolerant to the temperatures used in the processing. The gate region105 with the dummy polysilicon is defined at block 835. Photoresist isgenerally deposited on the dummy polysilicon layer. The photoresist ismasked and exposed, and either exposed or unexposed portions of thephotoresist are removed depending on the type of photoresist used. Thedummy polysilicon layer, the metal layer 115, and gate oxide layer 110is typically etched in the regions where the photoresist is removed todefine the gate length of the native PMOS device 100, 400. The remainingphotoresist is removed after the gate region 105 is formed.

At block 840, epitaxial layers of strained SiGe are deposited in thestrained regions 170 and 175 of the device 100, 400. For instance, thestrained regions, 170 and 175, are first defined and etched using maskand photoresist. Epitaxial layers of Si are deposited in the etchedregions with Ge atoms introduced during the epitaxial growth. The P-typeLDD regions 180 and 185 are implanted at block 845. For example, thesubstrate region 155 a in the strained regions 170 and 175 can be dopedwith boron atoms using an ion implantation process to provide therespective P-type LDD regions 180 and 185. The halo implants 160 and 165are implanted at block 850. The halo implants 160 and 165 are implantedat a 45 degree angle into the substrate region 155 a to form the haloimplants at a deeper region under the gate region 105 than the LDDregions, 160 and 165, as shown in FIGS. 1 and 4. The spacers, 125 and130, are deposited at block 855. The spacers, 125 and 130, are typicallydielectric material, formed of some type of nitride, such as Si3N4, oran oxide, such as SiO2. The spacers, 125 and 130, can be deposited usinglow-pressure chemical vapor deposition, for instance. Alternatively,block 840 can be processed after the formation of spacers at block 855.

The HDD regions 190 and 195 are implanted at block 860, for example, byan ion implantation process. For example, boron atoms can be acceleratedinto the strained regions 170 and 175 to form the heavily implanted HDDregions 190 and 195 respectively. At block 865, the dummy polysilicon ofthe gate region 105 is etched off and the contact metal layer 120 isdeposited on the metal layer 115 of the gate region 105.

The above processing steps are provided by way of example and notlimitation. Persons having ordinary skill in the semiconductorprocessing art will readily envision alternative processing techniquesto achieve the same device based on the present disclosure.

A METHOD OF PROCESSING A NATIVE PMOS ACCORDING TO A SECOND EMBODIMENT OFTHE PRESENT DISCLOSURE

FIG. 9 illustrates a flow chart for a method of processing a native PMOSdevice according to a second embodiment of the present disclosure. Thenative PMOS device 700 can be fabricated using, for example, CMOS logicfoundry technology with a minimum design rule of 20 nm. The processingof the native PMOS device 700 is similar to the processing of the device100, 400 as described above. Therefore, only differences between theprocessing steps of the native PMOS device 700 and the native PMOSdevice 100 are to be described in further detail.

As shown in FIG. 9, a dummy polysilicon is deposited at block 920 as adummy gate. The dummy gate can be replaced at the end of the processingof the native PMOS device 700 with the gate region 105 of the nativePMOS device 700.

At block 950, the raised regions 790 and 795 are formed, for example, bydepositing epitaxial layers of Si. The raised regions 790 and 795 areheavily doped with p-type carriers, for example, by ion implantation ofthe deposited Si epitaxial layers or by in situ doping, i.e., dopingwith p-type material during the deposition of the Si epitaxial layers.Block 950 can be combined with the deposition of strained SiGe layers atblock 930 and the combined process can follow the formation of spacersat block 945.

At block 955, the dummy gate between the spacers 125 and 130 of thedevice 700 is etched off. The gate oxide 110 is deposited at block 960,the metal layer 115 is deposited at block 965 and the contact metallayer is deposited at block 960.

The above processing steps are provided by way of example and notlimitation. Persons having ordinary skill in the semiconductorprocessing art will readily envision alternative processing techniquesto achieve the same device based on the present disclosure.

DIFFERENT EXEMPLARY CONFIGURATIONS OF A NATIVE PMOS ACCORDING TO ANEMBODIMENT OF THE PRESENT DISCLOSURE

FIGS. 10-12 show different exemplary configurations of a native PMOSdevice according to embodiments of the present disclosure. For example,the configuration shown in FIG. 10-12 can correspond to thecross-sectional view of the native PMOS device 100, 400, 700 shown inFIG. 1, FIG. 4 or FIG. 7, respectively. In FIGS. 10-12, the N-well 1045has an inner perimeter 1010 and an outer perimeter 1020. Referring toFIG. 10, the active area 107 does not overlap the N-well 1045. The innerperimeter 1010 completely laterally surrounds the active area 107 in thetwo-dimensional representation of FIG. 10. For instance, providing theactive area 107 within the inner perimeter 1010 of the native PMOSdevice 100, 400, 700 can reduce the junction capacitance of the nativePMOS device 100, 400, 700. Referring to FIG. 1, for instance, N-well 145does not extend beneath the source region 101 and N-well 146 does notextend beneath the drain region 102.

In FIG. 11, the active region 107 overlaps the N-well 1045 near themetal gate endcaps 1120 a and 1120 b, as indicated by the shadedoverlapping regions 1110 a and 1110 b. For instance, overlapping theN-well 1045 and the active region 107 near the metal gate endcaps 1110 aand 1120 b can reduce the source-to-drain leakage current.

In FIG. 12, the active region 107 overlaps the N-well 1045 at all edgesof the active region 107, as indicated by the shaded overlapping region1210. For example, overlapping the N-well 1045 and the active region 107at all edges of the active region 107 can substantially reduce theleakage path between the source and drain regions of the native PMOSdevice 100, 400, 700.

CONCLUSIONS

It is to be appreciated that the Detailed Description section, and notthe Abstract section, is intended to be used to interpret the claims.The Abstract section can set forth one or more, but not all exemplaryembodiments, of the present disclosure, and thus, are not intended tolimit the present disclosure and the appended claims in any way.

The present disclosure has been described above with the aid offunctional building blocks illustrating the implementation of specifiedfunctions and relationships thereof. The boundaries of these functionalbuilding blocks have been arbitrarily defined herein for the convenienceof the description. Alternate boundaries can be defined so long as thespecified functions and relationships thereof are appropriatelyperformed.

It will be apparent to those skilled in the relevant art(s) that variouschanges in form and detail can be made therein without departing fromthe spirit and scope of the present disclosure. Thus, the presentdisclosure should not be limited by any of the above-described exemplaryembodiments, but should be defined only in accordance with the followingclaims and their equivalents.

What is claimed is:
 1. A semiconductor device, comprising: a deep wellregion, having a first conductivity type, dividing a substrate into afirst substrate region having the first conductivity type and a secondsubstrate region having a second conductivity type different from thefirst conductivity type; a first region having a raised portion in thefirst substrate region, a top side of the raised portion being raisedabove a top side of the first substrate region; a second region; and athird region, between the first region and the second region, laterallydisplaced from the raised portion.
 2. The semiconductor device of claim1, wherein the first region further comprises a strained portionpositioned in the first substrate region, and wherein a sub-portion ofthe raised portion is positioned in the strained portion.
 3. Thesemiconductor device of claim 1, wherein the first region furthercomprises a strained portion, positioned in the first substrate region,having the first conductivity type, and wherein a sub-portion of theraised portion, positioned in the strained portion, has a thirdconductivity type greater than the first conductivity type and thesecond conductivity type.
 4. The semiconductor device of claim 3,wherein a vertical dimension of the strained portion is greater than orequal to a vertical dimension of the raised portion.
 5. Thesemiconductor device of claim 3, wherein the first region furthercomprises a doped portion having a fourth conductivity type differentfrom the first conductivity type, the second conductivity type, and thethird conductivity type, wherein a sub-portion of the doped portion ispositioned in the strained portion, and wherein a second sub-portion ofthe doped portion extends out from the strained portion.
 6. Thesemiconductor device of claim 3, wherein the strained portion comprisesa silicon germanium material.
 7. The semiconductor device of claim 5,wherein the third region is laterally displaced from the raised portionby the doped portion.
 8. The semiconductor device of claim 1, furthercomprising an isolation region, and wherein the raised portion is in atleast partial contact with the isolation region.
 9. The semiconductordevice of claim 1, wherein the second region comprises: a second raisedportion in the first substrate region; a strained portion positioned inthe first substrate region; and a sub-portion of the second raisedportion positioned in the strained portion.
 10. The semiconductor deviceof claim 1, wherein the third region comprises: a first layer having afirst thickness and a high-k dielectric material selected from the groupconsisting of hafnium dioxide and zirconium dioxide; a second layerhaving a second thickness greater than the first thickness and having ametal selected from the group consisting of tungsten and titanium; and athird layer having a third thickness greater than the second thicknessand having a contact metal selected from the group consisting ofaluminum and copper.
 11. The semiconductor device of claim 1, whereinthe semiconductor device is characterized as having a threshold voltageof approximately zero volts.
 12. A P-type metal oxide semiconductor(PMOS) device, comprising: a deep well region, having a firstconductivity type, dividing a substrate into a first substrate regionhaving the first conductivity type and a second substrate region havinga second conductivity type different from the first conductivity type; afirst region having a raised portion in the first substrate region, atop side of the raised portion being raised above a top side of thefirst substrate region; a second region; and a third region, between thefirst region and the second region, laterally displaced from the raisedportion.
 13. The PMOS device of claim 12, wherein the first regionfurther comprises a strained portion, positioned in the first substrateregion, having the first conductivity type, and wherein a sub-portion ofthe raised portion, positioned in the strained portion, has a thirdconductivity greater than the first and second conductivities.
 14. ThePMOS device of claim 13, wherein the first region further comprises adoped portion having a fourth conductivity type different from the firstconductivity type, the second conductivity type, and the thirdconductivity type, wherein a sub-portion of the doped portion ispositioned in the strained portion; and wherein a second sub-portion ofthe doped portion extends out from the strained portion.
 15. The PMOSdevice of claim 13, wherein the strained portion comprises a silicongermanium material.
 16. The PMOS device of claim 12, further comprisingan isolation region, and wherein the raised portion is in at leastpartial contact with the isolation region.
 17. The PMOS device of claim12, wherein the third region comprises: a first layer having a firstthickness and a high-k dielectric material selected from the groupconsisting of hafnium dioxide and zirconium dioxide; a second layerhaving a second thickness greater than the first thickness and having ametal selected from the group consisting of tungsten and titanium; and athird layer having a third thickness greater than the second thicknessand having a contact metal selected from the group consisting ofaluminum and copper.
 18. A semiconductor device, comprising: a wellregion, having a first conductivity type, dividing a substrate into afirst substrate region having the first conductivity type and a secondsubstrate region having a second conductivity type different from thefirst conductivity type; a source region having a raised portion and astrained portion in the first substrate region, a sub-portion of theraised portion, positioned in the strained portion, having a thirdconductivity type greater than the first conductivity type and thesecond conductivity type; a drain region; and a gate region, between thesource region and the drain region, laterally displaced from the raisedportion.
 19. The semiconductor device of claim 18, wherein the strainedportion comprises a compound semiconductor material.
 20. Thesemiconductor device of claim 18, wherein a vertical dimension of thestrained portion is greater than or equal to a vertical dimension of theraised portion.